 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product PRODUCT FEATURES SEL FREQUENCY TABLE CPU 60.0 66.6 PCI 30.0 33.3 0 1 * * * * * * * * * * * * * * Supports Pentium & Pro CPUs. 4 CPU clocks up to 8 loads. Up to 8 SDRAM clocks for 2 DIMs. Supports Power Savings Frequencies. 7 PCI synchronous clocks. Optional common or mixed supply mode: (Vdd = Vddq3 = Vddq2 = 3.3V) or (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V) < 250ps skew CPU and SDRAM clocks. < 250ps skew among PCI clocks. I2C 2-Wire serial interface Programmable registers featuring: - enable/disable each output pin - mode as tri-state, test, or normal - 24/48 MHz selections 1 IOAPIC clock for multiprocessor support. 48-pin SSOP package CONNECTION DIAGRAM IMISC670 REF1 REF0 Vss Xin Xout MODE Vddq3 PCICLK_F PCICLK0 Vss PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd N/C (See note 1) Vddq2 IOAPIC0 PWR_DWN# Vss CPUCLK0 CPUCLK1 Vddq2 CPUCLK2 CPUCLK3 Vss SDRAM0 SDRAM1 Vddq3 SDRAM2 SDRAM3 Vss SDRAM4 SDRAM5 Vddq3 SDRAM6/CPU_STOP# SDRAM7/PCI_STOP# Vdd BLOCK DIAGRAM 3 Xin Xout REF OSC Vddq2 IOAPIC0 REF0:1 PCICLK5 Vss SEL SDATA SDCLK Vddq3 48/24MHZ 48/24MHZ Vss SDATA SDCLK Vddq2 4 Vddq3 CPUCLK0~3 8 6 SDRAM0~7 PCICLK0~5 SEL PLL1 dly PCI_STOP# CPU_STOP# PWR_DWN# MODE PCICLK_F 48/24MHZ PLL2 48/24MHZ Note 1: N/C is a no connect pin. IMI product does not require CPU 3.3_2.5# select line to operate properly at 2.5 volts. This pin may be connected externally to Vdd or Vss. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 1 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product PIN DESCRIPTION Xin, Xout - These pins form an on-chip reference oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 MHz). Xin may also serve as input for an externally generated reference signal. SEL - Standard frequency select input. It has internal pull-up. CPUCLK(0:3) - Low skew (<250 pS) clock outputs for host frequencies such as CPU, Chipset, Cache. Vddq2 is the supply voltage for these outputs. SDRAM(0:5) - Synchronous DRAM DIMs clocks. They are powered by Vddq3. SDRAM6/CPU_STOP# - If MODE=1, this pin is a Synchronous DRAM DIMs clock output powered by Vddq3. If MODE=0, this pin is a CPU_STOP# input signal, where a low level stops the CPU. However, SDRAM clocks will still be active. SDRAM7/PCI_STOP# - If MODE=1, this pin is a Synchronous DRAM DIMs clock output powered by Vddq3. If MODE=0, this pin is a PCI_STOP# input signal, where a low level stops the PCI clocks. MODE - A low level on this pin causes pins 26, and 27 to be power management inputs PCI_STOP#, and CPU_STOP# respectly. A high level on this pin causes pins 26, and 27 to be clock output signals SDRAM7, and SDRAM6 respectively. It has an internal pull-up resistor. PCICLK(0:5) - Low skew (<250pS) clock outputs for PCI frequencies. These buffers voltage level is controlled by Vddq3 PCICLK_F - A PCI clock output that does not stop until in power down mode. It is synchronous with other PCI clocks. REF(0:1) - Buffered outputs of on-chip reference. IOAPIC0 - Buffered output of 14.3MHZ multiprocessor support. It is powered by Vddq2. for PWR_DWN# - Power down pin. When this pin is asserted low, the IC is in shutdown mode where all circuitry is turned off including VCO, crystal buffer and 2 PCICLK_F. It has an internal pull-up. The I C interface is disabled with the PWR_DWN# pin is low. 48/24MHz(0:1) - Programmable 48 MHZ or 24 MHZ clock outputs. SDATA - serial data of I C 2-wire control interface. Has internal pull-up resistor. SDCLK - serial clock of I C 2-wire control interface. Has internal pull-up resistor. Vss - Ground pins for the chip. Vdd - Power supply pins for analog circuit and core logic. Vddq3 - Power supply pins for 3.3V IO pins. Vddq2 - Power supply pins for 2.5V/3.3V IO pins. 2 2 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 2 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product POWER MANAGEMENT FUNCTIONS All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. When MODE=0, pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively (when MODE=1, these functions are not available). A particular output is enabled only when both the serial interface and these pins indicate that it should be enabled. The IMISC670 clocks may be disabled according to the following table in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 0.2 mS for the VCOs to stabilize prior to assuming the clock periods are correct. The CPU and PCI clocks transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_DWN# 0 1 1 1 1 CPUCLK LOW LOW LOW 66/60 MHZ 66/60 MHZ PCICLK LOW LOW 33/30 MHZ LOW 33/30 MHZ OTHER CLKs LOW RUNNING RUNNING RUNNING RUNNING XTAL & VCOs OFF RUNNING RUNNING RUNNING RUNNING POWER MANAGEMENT TIMING PCICLK_F PCI_STOP# PCICLK(0:5) CPU_STOP# CPUCLK(0:3) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 3 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product 2-WIRE I2C CONTROL INTERFACE The 2-wire control interface implements a write only slave interface. The IMISC670 cannot be read back. Subaddressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2wire control interface allows each clock output to be individually enabled or disabled. It also allows 24/48 MHZ frequency selection and test mode enable. During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first. The IMISC670 will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on the SDATA wire following reception of each byte. The IMISC670 will not respond to any other control 2 interface conditions. The I C interface is disabled when the PWR_DWN# pin is low. Previously set control registers are retained. SERIAL CONTROL REGISTERS NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated. Following the acknowledge of the Address Byte (D2), two additional bytes must be sent: 1) "Command Code " byte, and 2) "Byte Count" byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledged. Byte 0: Function Select Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 1 0 0 Pin# * * * * 23 22 Description Reserved, Don't set Reserved, Don't set Reserved, Don't set Reserved, Don't set 48/24 Mhz 48/24 Mhz Bit1 Bit0 1 1 Tri-State 1 0 Reserved 0 1 Test Mode 0 0 Normal IMPORTANT NOTE Reserved bits are intended for possible future functions. It is important that they be left at their Power Up logic levels at all times. Otherwise data sheet specifications cannot be guaranteed. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 4 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product SERIAL CONTROL REGISTERS (Cont.) Function Table Function Description Tri-State Test Mode Normal SEL=1 Normal SEL=0 Outputs Ref Hi-Z Tclk 14.318 14.318 CPU Hi-Z Tclk/2 66 60 PCI Hi-Z Tclk/4 CPU/2 CPU/2 SDRAM Hi-Z Tclk/2 CPU CPU IOAPIC Hi-Z Tclk 14.318 14.318 24MHZ Hi-Z Tclk/4 24 24 48MHZ Hi-Z Tclk/2 48 48 Notes: 1. Tclk is a test clock over driven on the Xin input during test mode. 2. The frequency ratio Fout/Fin for the USB output is 3.35294. Byte 1: CPU, 48/24 MHz Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 x x 1 1 1 1 Pin# 23 22 38 39 41 42 Description 48/24 MHz enable/Stopped 48/24 MHz enable/Stopped Reserved Reserved CPUCLK3 enable/Stopped CPUCLK2 enable/Stopped CPUCLK1 enable/Stopped CPUCLK0 enable/Stopped Byte 2: PCI Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x 1 1 1 1 1 1 1 Pin# 8 16 14 13 12 11 9 Description Reserved PCICLK_F enable/Stopped PCICLK5 enable/Stopped PCICLK4 enable/Stopped PCICLK3 enable/Stopped PCICLK2 enable/Stopped PCICLK1 enable/Stopped PCICLK0 enable/Stopped INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 5 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product SERIAL CONTROL REGISTERS(Continued) Byte 3: SDRAM Clock Register ( 1 = enable, 0 = Stopped ) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 26 27 29 30 32 33 35 36 Description SDRAM7 enable/Stopped SDRAM6 enable/Stopped SDRAM5 enable/Stopped SDRAM4 enable/Stopped SDRAM3 enable/Stopped SDRAM2 enable/Stopped SDRAM1 enable/Stopped SDRAM0 enable/Stopped Byte 4: Additional SDRAM Clock Register (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x x x x x x x Pin# Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 5: Peripheral Control (1 = enable, 0 = Stopped) Bit 7 6 5 4 3 2 1 0 @Pup x x 1 1 x x 1 1 Pin# 45 1 2 Description Reserved Reserved Reserved IOAPIC0 enable/Stopped Reserved Reserved REF1 enable/Stopped REF0 enable/Stopped INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 6 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product SERIAL CONTROL REGISTERS(Continued) Byte 6: Reserved Register Bit 7 6 5 4 3 2 1 0 @Pup x x x x x x x x Pin# Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Byte 7: Frequency Control If the three LSBs of this register are 111 (as at power up), the frequency is controlled by the SEL package pin. Note that if this pin is open, the internal pull-up will select 66 MHz. Otherwise, the CPU clock frequency is controlled by F_SEL(0:2). Bit 7 6 5 4 3 2 1 0 @Pup x x x x x 1 1 1 Description Reserved Reserved Reserved Reserved Reserved F_SEL2 F_SEL1 F_SEL0 FSEL2 0 0 0 0 1 1 1 1 FSEL1 0 0 1 1 0 0 1 1 FSEL0 0 1 0 1 0 1 0 1 FREQUENCY Reserved Reserved Reserved 33 MHz 50 MHz 55 MHz 60 MHz From SEL pin INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 7 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product MAXIMUM RATINGS This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout) -0.3V 0.3V -65C to + 150C -55C to +125C 7V ELECTRICAL CHARACTERISTICS Characteristic Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol VIL VIH IIL IIH VOL VOH Ioz Idd Isdd ISC Min 2.0 Typ Max 0.8 -66 5 0.4 10 90 150 Units Vdc Vdc A A Vdc Vdc A mA A mA Conditions - 2.4 25 - All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) CPU = 66.6 MHz, PCI = 33.3 MHz 1 output at a time - 30 seconds VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.375V to 2.9V, TA = 0C to +70C INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 8 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product SWITCHING CHARACTERISTICS Characteristic Output Duty Cycle CPU to PCI Offset Buffer out Skew All CPU and PCI Buffer Outputs Period Adjacent Cycles Jitter Spectrum 20 dB Bandwidth from Center Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion Symbol tOFF tSKEW P BWJ Vover VRBE 0.7 Min 45 1 Typ 50 Max 55 4 250 +250 500 1.5 2.1 Units % ns ps ps KHz V V 22 ohms @ source of 8 inch PCB run to 15 pf load note1 Conditions Measured at 1.5V 15 pf Load Measured at 1.5V 15 pf Load Measured at 1.5V - VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.375V to 2.9V, TA = 0C to +70C note 1: Ring Back must not enter this range. TYPE 1 BUFFER CHARACTERISTICS FOR CPUCLK(0:3) Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH IOH IOL IOL TRFmin TRFmax Min -91 -43 83 26 0.4 Typ -131 -62 119 38 Max -183 -87 167 53 1.5 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.0 V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.5V5% , TA = 0C to +70C TYPE 2 BUFFER CHARACTERISTICS FOR IOAPIC Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Min Between 0.4 V and 2.0 V Rise/Fall Time Max Between 0.4 V and 2.0 V Symbol IOH IOH IOL IOL TRFmin TRFmax Min -91 -43 83 26 0.4 Typ -131 -62 119 38 Max -183 -87 167 53 1.9 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.0 V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.5V5% , TA = 0C to +70C INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 9 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product TYPE 3 BUFFER CHARACTERISTICS FOR REF(1:2) and 48/24 MHz Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Symbol IOH IOH IOL IOL TRFmin TRFmax Min -40 -32 37 12 1.0 Typ -53 -42 47 15 Max -69 -53 58 19 2.0 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.0 V Vout = 1.2 V Vout = 0.3 V 10 pF Load 20 pF Load VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.5V5% , TA = 0C to +70C TYPE 4 BUFFER CHARACTERISTICS FOR REF0 and SDRAM(0:7) Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Symbol IOH IOH IOL IOL TRFmin TRFmax Min -94 -74 83 26 0.5 Typ -134 -106 119 38 Max -188 -148 167 53 2.0 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.0 V Vout = 1.2 V Vout = 0.3 V 20 pF Load 30 pF Load VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.5V5% , TA = 0C to +70C TYPE 5 BUFFER CHARACTERISTICS FOR PCICLK(0:5,F) Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Min Between 0.4 V and 2.4 V Rise/Fall Time Max Between 0.4 V and 2.4 V Symbol IOH IOH IOL IOL TRFmin TRFmax Min -94 -74 83 26 0.5 Typ -134 -106 119 38 Max -188 -148 167 53 2.0 Units mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.0 V Vout = 1.2 V Vout = 0.3 V 15 pF Load 30 pF Load VDD = VDDQ3 =3.3V 5%, VDDQ2 = 2.5V5% , TA = 0C to +70C INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 10 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product PCB LAYOUT SUGGESTION Via to VDD Via to GND plane Via to VCC plane VCC1 FB1 1 2 3 IMISC670 C12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C3 10F 4 5 6 7 C11 FB2 VCC2 C10 C13 10F C4 8 9 10 11 12 13 14 15 C9 C5 C6 16 17 18 19 20 21 22 23 24 C8 C7 This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1f) should always be used and placed close to their VDD pins. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 11 of 12 www..com SC670 I2C Clock Generator for Pentium Notebook Designs. Approved Product PACKAGE DRAWING AND DIMENSIONS 48 PIN SSOP OUTLINE DIMENSIONS C INCHES L E H SYMBOL A A1 A2 B D A2 A1 B e A C a MILLIMETERS MAX 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 0.410 0.016 0.040 8 0.100 MIN 2.41 0.20 2.24 0.203 0.127 15.75 7.42 10.16 0.25 0.61 0 2.16 NOM 2.59 0.31 2.29 0.254 15.88 7.52 0.635 BSC 10.31 0.33 0.81 5 2.36 10.41 0.41 1.02 8 2.54 MAX 2.79 0.41 2.34 0.343 0.254 16.00 7.59 MIN 0.095 0.008 0.088 0.008 0.005 0.620 0.292 0.400 0.10 0.024 0 0.085 NOM 0.102 0.012 0.090 0.010 0.625 0.296 0.025 BSC 0.406 0.013 0.032 5 0.093 D E e H a L a X ORDERING INFORMATION Part Number IMISC670DYB Note: Marking: Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Example: IMI SC670DYB Date Code, Lot # Flow B = Commercial, 0C to + 70C Package Y = SSOP Revision IMI Device Number IMISC670DYB Purchase of I2C components of International Microcircuits, Inc. or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.4 6/20/97 Page 12 of 12 |
Price & Availability of SC670
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |